Generally, during the formation of a multi layer metal wiring, a technology of a via is used for connecting a bottom metal wiring to a top metal wiring.
FIG. 1 is a diagram showing a method for forming a field programmable gate array (FPGA) according to a prior art.
Referring to FIG. 1, after a first metal wiring M1 is formed, a first inter metal dielectric (IMD) 11 is deposited and the first IMD 11 is planarized through a chemical mechanical polishing (CMP).
Thereafter, after a first via hole to expose a surface of the first metal wiring M1 is formed by etching the first IMD 11 by using a via mask, a first via 12 filled inside of the first via hole is formed through a tungsten deposition and the CMP.
And then, a second metal wiring M2 connected to the first metal wiring M1 through the first via 12 is formed on the first via 12.
In the next step, a second IMD 13 is deposited on the second metal wiring M2; a second via hole and a second via 14 filled into the second via hole are formed; and a third metal wiring M3 connected to the second via 14 is formed.
Thereafter, a third IMD 15 is deposited on the third metal wiring M3, and a third via hole and a third via 16 which fills the third via hole are formed, and a fourth metal wiring M4 connected to the third via 16 is formed.
However, the above-mentioned multi-layer metal wiring manufacturing process, as shown in FIG. 1, has a problem that a manufacturing cost of a semiconductor device is excessively spent since an unnecessary process and masks, e.g., the number of via masks required is smaller than that of metal wiring masks by one, are used.